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CompactPCI Plus – why the world needs another backplane standard
There are already many backplane standards in existence, so why is another one being developed? Andreas Lenkisch and Keith Reynolds take a closer look at CompactPCI Plus.
Many industrial embedded computer systems since the mid 1990s have been built around the CompactPCI specification, which was developed by PICMG (the PCI Industrial Computer Manufacturers Group) as a high-performance version of the desktop PCI specification. Featuring rugged 3U or 6U Eurocard formats and twice as many slots as the standard desktop PCI, CompactPCI offered a packaging scheme that was much better suited to use in industrial systems.
However, CompactPCI is proving to be inadequate for many applications as it provides no serial interfaces such as PCI Express, SATA, Ethernet or USB via the backplane. In addition, the interface chipsets that support the parallel PCI bus will slowly but surely become obsolete in the next few years.
The originally planned successor to CompactPCI - CompactPCI Express - lacks decisive features such as support for SATA, USB and Ethernet. Furthermore, in CompactPCI Express the number of rear I/O connections is too small, and a special bridge slot is required for backwards compatibility with CompactPCI.
To address these and other limitations, PICMG is now developing a new standard - CompactPCI Plus (CPLUS.0) - which is intended to be more flexible and cost-effective than CompactPCI, while providing a smooth migration path that will enable continued use of the CompactPCI ecosystem.
Many industrial embedded computer systems since the mid 1990s have been built around the CompactPCI specification, which was developed by PICMG (the PCI Industrial Computer Manufacturers Group) as a high-performance version of the desktop PCI specification. Featuring rugged 3U or 6U Eurocard formats and twice as many slots as the standard desktop PCI, CompactPCI offered a packaging scheme that was much better suited to use in industrial systems.
However, CompactPCI is proving to be inadequate for many applications as it provides no serial interfaces such as PCI Express, SATA, Ethernet or USB via the backplane. In addition, the interface chipsets that support the parallel PCI bus will slowly but surely become obsolete in the next few years.
The originally planned successor to CompactPCI - CompactPCI Express - lacks decisive features such as support for SATA, USB and Ethernet. Furthermore, in CompactPCI Express the number of rear I/O connections is too small, and a special bridge slot is required for backwards compatibility with CompactPCI.
To address these and other limitations, PICMG is now developing a new standard - CompactPCI Plus (CPLUS.0) - which is intended to be more flexible and cost-effective than CompactPCI, while providing a smooth migration path that will enable continued use of the CompactPCI ecosystem.
Backplane architecture
In developing the new specification, high priority has been given to both cost-effectiveness and modularity. The architecture is star-configured, without a separate hub slot and without management. The central star point is the CPU slot. Neither coding nor management are necessary, but these functions are not ruled out and can be added at any time if the application calls for them. The necessary contacts in the connector are reserved so that any future expansion can be easily implemented.
Similarly, all protocols are available simultaneously on the connector, on the CPU slot and on the peripheral slots. No contacts in the connector have any alternative use, i.e. none are used for multiple functions. This reduces costs as no coding is required. Moreover, it facilitates modularity and above all flexibility. The main benefit lies in the universality of the peripheral slots; they are all the same, regardless of whether communication is via PCIe, Ethernet or USB and whether or not a storage medium is inserted.
The CPU slot, as defined by CompactPCI Plus, offers support for the following protocols:
• seven PCIe lanes (4x)
• one PCIe lane (16x), for graphics or general high-bandwidth use
• eight differential PCIe clock outputs for spread spectrum mode
• eight SATA ports
• eight USB II ports (1 differential pair per port)
• eight USB III ports (2 differential pairs per port)
• eight Ethernet 10/100/1000Base-T ports.
Eight peripheral slots can thus be supported, on which all signals are present simultaneously. This enables standard backplanes to be factory configured, which is important where small batches or prototypes are concerned.
If the chipset used can configure the 16x link as four 4x links, then up to 11 slots with 4x links can be connected to the CPU without a switch. Should these 11 slots still not be sufficient and if data throughput is not too high, up to 44 slots can be configured as 1x links in one system, if the chipset permits. Even with a 1x link and PCIe GenII, the data transfer rate of 500 Mb/s is already twice as high as with a CPCI 66MHz/64-bit system with a maximum of 4 slots, and probably sufficient for almost all uses.
The limitations are more realistically the mechanics and length of the electrical lines, but about 20 slots can certainly be realised. And where a switch is still required, the fat pipe slot with the 16x link can serve as a bridgehead. The choice of connector system and distribution of signals on individual connector blocks allow a bridge to be inserted from the rear without loss of slots and without electrical complications.
Similarly, all protocols are available simultaneously on the connector, on the CPU slot and on the peripheral slots. No contacts in the connector have any alternative use, i.e. none are used for multiple functions. This reduces costs as no coding is required. Moreover, it facilitates modularity and above all flexibility. The main benefit lies in the universality of the peripheral slots; they are all the same, regardless of whether communication is via PCIe, Ethernet or USB and whether or not a storage medium is inserted.
The CPU slot, as defined by CompactPCI Plus, offers support for the following protocols:
• seven PCIe lanes (4x)
• one PCIe lane (16x), for graphics or general high-bandwidth use
• eight differential PCIe clock outputs for spread spectrum mode
• eight SATA ports
• eight USB II ports (1 differential pair per port)
• eight USB III ports (2 differential pairs per port)
• eight Ethernet 10/100/1000Base-T ports.
Eight peripheral slots can thus be supported, on which all signals are present simultaneously. This enables standard backplanes to be factory configured, which is important where small batches or prototypes are concerned.
If the chipset used can configure the 16x link as four 4x links, then up to 11 slots with 4x links can be connected to the CPU without a switch. Should these 11 slots still not be sufficient and if data throughput is not too high, up to 44 slots can be configured as 1x links in one system, if the chipset permits. Even with a 1x link and PCIe GenII, the data transfer rate of 500 Mb/s is already twice as high as with a CPCI 66MHz/64-bit system with a maximum of 4 slots, and probably sufficient for almost all uses.
The limitations are more realistically the mechanics and length of the electrical lines, but about 20 slots can certainly be realised. And where a switch is still required, the fat pipe slot with the 16x link can serve as a bridgehead. The choice of connector system and distribution of signals on individual connector blocks allow a bridge to be inserted from the rear without loss of slots and without electrical complications.
Connector system
The connector system for CompactPCI Plus (Fig. 1) had to satisfy a number of key development goals, the most important of which were: a bandwidth greater than 10 Gb/s, high signal density, sufficiently wide routing channel between the pins, high current-carrying capacity of approximately 1A for the power supply, short press-in pins for rear I/O from both sides of the backplane, and mirror-symmetrical layout of signal pins and/or no predestination of signal/GND allocation.
Fig. 1. Connector system for CompactPCI Plus.
The high data rate for the connectors is necessary for the future viability of the CompactPCI specification. While such high data rates are rarely needed in industrial computing today, the demands of future applications are unknown, and it is essential that the connector does not become a system bottleneck.
A further requirement of the connector was that a sufficiently high number of differential pairs be made available on a 100mm euroboard. The width of the routing channel - that is the clearance between the drilled holes for the connector on the backplane - has a major influence on the routing of the backplane and also affects the number of layers required, and hence the cost of the backplane. This requirement is contrary to that for a higher signal density, so the correct balance has to be struck between the two factors.
The highest possible current-carrying capacity for the signal pins is necessary so that the power can be supplied via the signal connector. This means that no separate power connector is required, which in turn cuts costs and affords more space for signals on the 100mm euroboard.
A further requirement of the connector was that a sufficiently high number of differential pairs be made available on a 100mm euroboard. The width of the routing channel - that is the clearance between the drilled holes for the connector on the backplane - has a major influence on the routing of the backplane and also affects the number of layers required, and hence the cost of the backplane. This requirement is contrary to that for a higher signal density, so the correct balance has to be struck between the two factors.
The highest possible current-carrying capacity for the signal pins is necessary so that the power can be supplied via the signal connector. This means that no separate power connector is required, which in turn cuts costs and affords more space for signals on the 100mm euroboard.
Smooth transition
As CompactPCI and CompactPCI Plus are neither mechanically nor electrically compatible, the draft PICMG 2.30 CPLUS I/O specification has been developed to create a smooth migration path from CompactPCI into the future of the serial protocol. The CPU defined to this specification acts as mediator between the old and new worlds, linking the conventional, parallel 32-bit CompactPCI bus with the new slots, defined to CompactPCI Plus for the serial protocols.
The CPU designed to PICMG 2.30 CPLUS I/O provides not only the serial SATA, USB and Ethernet protocols on the CompactPCI P2 connector, but also PCIe. The backplane, also new and defined to PICMG 2.30 CPLUS I/O, links these signals from the P2 connector to the peripheral CompactPCI Plus slots.
Fig. 2 shows an example of a hybrid backplane for migrating from the conventional slots, supported by the parallel PCI bus, to pure, serial CPCI Plus slots. It can be clearly seen that the peripheral slots require, unlike in CompactPCI, only a relatively small, low-cost connector with six rows of contacts, which carries power, high-speed signals and any necessary monitoring and control lines.
The CPU designed to PICMG 2.30 CPLUS I/O provides not only the serial SATA, USB and Ethernet protocols on the CompactPCI P2 connector, but also PCIe. The backplane, also new and defined to PICMG 2.30 CPLUS I/O, links these signals from the P2 connector to the peripheral CompactPCI Plus slots.
Fig. 2 shows an example of a hybrid backplane for migrating from the conventional slots, supported by the parallel PCI bus, to pure, serial CPCI Plus slots. It can be clearly seen that the peripheral slots require, unlike in CompactPCI, only a relatively small, low-cost connector with six rows of contacts, which carries power, high-speed signals and any necessary monitoring and control lines.
Fig. 2. Schematic of a hybrid backplane for soft transition from parallel to serial architecture.
The use of such hybrid backplanes means that it is not necessary for 'old' CompactPCI boards to be redesigned immediately; they can be produced for as long as the chips for the parallel PCI bus continue to be available. New designs should, however, be drafted on the basis of CompactPCI Plus.
Fig. 3. 3U subrack system with ATX power supply for use as a CompactPCI Plus development unit.
For further information, visit www.schroff.co.uk and www.picmg.org.
Author profiles:
Contact details for publication:
www.schroff.co.uk
schroff.uk@pentair.com
Tel: +44 (0)1442 218726
www.schroff.co.uk
schroff.uk@pentair.com
Tel: +44 (0)1442 218726
Press inquiries to:
Keith Reynolds
Schroff UK Ltd
keith.reynolds@pentair.com
Tel: +44 (0)1442 218726
or
Rick Bauling
RJB Communications
rbauling@rjbcoms.com
Tel: +44 (0)1234 782255
2nd July 2009, Ref. SC178A/uk915
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