The current CompactPCI standard provides no serial interfaces such as PCI Express, Serial Advanced Technology Attachment (SATA), Ethernet or USB via the backplane. The originally planned successor, CompactPCI Express, lacks decisive features such as support for SATA, USB and Ethernet. Furthermore a special bridge slot is required for backwards compatibility with CompactPCI. In CompactPCI Express the number of rear I/O connections is also too small. The new standard, CompactPCI Plus, is intended to compensate for these and other limitations.

There are already many standards for backplanes such as CompactPCI, CompactPCI Express, AdvancedTCA and MicroTCA, VXS and VPX. So why does the world need another new standard? Why indeed does it need a new backplane specification at all? There are two principal arguments in favour:

• The interface chipsets that support the parallel PCI bus will slowly but surely become obsolete in the next few years.
• We need a successor to CompactPCI that allows a soft transition to a new specification if we are to be able to go on using the CompactPCI ecosystem for much longer, and it needs to be more cost-effective and more flexible than CompactPCI.

The urgent need for a change to a new, future-proof system can be seen from the current stage of development of serial data transport mechanisms. The first generation of PCI Express, successor to the parallel PCI bus, was adopted back in 2002 and the second generation in 2006; work is now in progress on the third. The situation looks similar for SATA, the standard protocol for data storage systems. So it is high time that we prepare for the future. CompactPCI Plus (Cplus.0) is the future of industrial embedded computer systems. And the PICMG 2.30 CPLUS I/O specification allows a "soft" migration path from CompactPCI to the future. Both specifications - each still at the draft stage - represent the logical further development of CompactPCI, supported by today's data transport mechanisms - PCI Express (PCIe), SATA, USB II & III and Ethernet Base-T.

High priority in developing the new specification was given to cost-effectiveness and modularity. The architecture is star-configured, without a separate hub slot and without management. The central star point is the CPU slot. Neither coding nor management are necessary, but nor is either ruled out. If required, these functions can be added at any time if the application calls for them. The necessary contacts in the connector are reserved so that future expansion can be simply realised. Similarly, all protocols are available simultaneously on the connector, on the CPU slot and on the peripheral slots. No contacts in the connector have any alternative use, i.e. none are used for multiple functions. This reduces costs as no coding is required. Moreover it facilitates modularity and above all flexibility. The main benefit lies in the universality of the (peripheral) slots. They are all the same, regardless of whether communication is via PCIe, Ethernet or USB and whether or not a storage medium is inserted.

The CPU slot, defined to CompactPCI Plus, offers support for the following protocols:

• seven 4x PCIe lanes (4x)
• one 16x PCIe lane (16x), for graphics or general high-bandwidth use
• eight differential PCIe clock outputs for spread spectrum mode
• eight SATA ports
• eight USB II ports (1 differential pair per port)
• eight USB III ports (2 differential pairs per port)
• eight Ethernet 10/100/1000Base-T ports

Eight peripheral slots can thus be supported, on which all signals are present simultaneously. Standard backplanes are thus factory configured, which is important where small batches or prototypes are concerned. With CompactPCI Plus there is thus one more slot on standard backplanes than on conventional CompactPCI backplanes. Without interfering with the specification, the possibility of other configurations is also planned. Since it is rare that all protocols are needed at once on a single slot, these can be split. It is thus conceivable to decouple the memory bank with up to 8 hard disks in RAID configuration from the PCIe unit, so freeing up all eight PCIe slots for use by the application. Should this not suffice, other configurations are possible without a bridge or switch. This will make CompactPCI Plus more cost-effective than CompactPCI.
If the chipset can also configure the 16x link as four 4x links, then 11 slots with 4x links can be connected to the CPU without a switch. Should these 11 slots still not be sufficient and if data throughput is not too high, up to 44 slots can be configured as 1x links in one system, if the chipset permits. Even with a 1x link and PCIe GenII the data transfer rate of 500 Mb/s is already twice as high as with a CPCI 66MHz/64-bit system with a maximum of 4 slots, and probably sufficient for almost all use cases. The limitations are more realistically the mechanics and length of the electrical lines, but about 20 slots can be realised for sure. And where a switch is still required, the fat pipe slot with the 16x link can serve as a bridgehead. The choice of connector system and distribution of signals on individual connector blocks allow a bridge to be inserted from the rear without loss of slots and without electrical complications.

The AirMax VS connector system (Fig. 1) from FCI was chosen for CompactPCI Plus. This connector was subjected to a series of stringent requirements to ensure that the development goals of the specification could be achieved. In brief, the most important of these are as follows:

• Bandwidth > 10Gbps
• high signal density
• sufficiently wide routing channel between the pins
• high current-carrying capacity for the power supply, approx. 1 A
• short press-in pins for rear I/O from both sides on the backplane
• mirror-symmetrical layout of signal pins and/or no predestination of signal/GND allocation

The high data rate that the connectors must be able to carry is necessary for the future viability of the specification. If the data rate is later increased in the protocol specifications, the connector must not become a system bottleneck. While such high data rates are rarely needed in industrial computing, we do not know what demands will be made by applications in the future. Image-processing systems for machine safety or quality assurance are already familiar today that require 'rather more' bandwidth. At any rate, limitations that are evident today are to be avoided in order to give the new system the longest possible life. That is one of the axiomatic principles for the development of the new specification.

A further demand made of the connector was that a sufficiently high number of differential pairs be made available on a 100 mm euroboard. With the AirMax VS connector 184 differential pairs are possible. The width of the routing channel - that is the clearance between the drilled holes for the connector on the backplane - has a major influence on the routing of the backplane and also affects the number of layers required, and hence the cost of the backplane. This requirement is contrary to that for a higher signal density. The correct balance must be struck between the two factors.

The highest possible current-carrying capacity for the signal pins is necessary so that the power can be supplied via the signal connector. Then no separate power connector is required, which in turn cuts costs and affords more space for signals on the 100 mm euroboard. A power supply with a single output of +12 V was selected. For supply to the CPU and other ICs, point-of-load controllers are required on the board to provide the necessary core voltages and also the other voltages required. Thus the PSU of a CompactPCI Plus system is substantially simpler and lower in cost.

From a technical point of view, high-speed connectors can no longer be fitted with long pins for handover connectors on the rear. To do so would seriously impair signal integrity. There remains only the possibility of pressing connectors from both sides into the backplane. The pins with the press-in zone are 1.6 mm long in the chosen connector. Thus the backplane must be only at least about 3.6 mm thick for rear I/O.

How can the CompactPCI ecosystem continue and a soft transition be made to the new specification? The slots are neither mechanically nor electrically compatible, so another solution must be defined.

The PICMG 2.30 CPLUS I/O specification, currently still at the draft stage, opens up a soft migration path from CompactPCI into the future of the serial protocol. The CPU defined to this specification acts as mediator between the old and new worlds. Its slot links the conventional, parallel 32-bit (Compact) PCI bus with the new slots, defined to CompactPCI Plus for the serial protocols. Thus both "old" and "new" boards can work together in perfect harmony in a single system.

As is sometimes already customary in CompactPCI, the CPU, designed to PICMG 2.30 CPLUS I/O, provides not only the serial SATA, USB and where necessary also Ethernet protocols on the CompactPCI P2 connector but also PCIe. The UHM (ultra-hard metric) B22 from 3M has been defined as the P2 connector. In terms of insertion and footprint it is compatible with the earlier P2 connector but can carry signals at rates of up to some 5 Gbps. This provides sufficient performance for the data rates currently used by the serial protocols, and existing CPUs can be made fit for the future with little design input. The backplane, also new and defined to PICMG 2.30 CPLUS I/O, links these signals from the P2 connector to the peripheral CompactPCI Plus slots. These are already equipped with the high-speed AirMax VS connector from FCI defined for CompactPCI Plus, which is designed for transfer rates of up to 12.5 Gbps.

There should thus be sufficient headroom for future performance enhancements in the protocol specifications, so that CompactPCI Plus will be able to remain the standard for industrial embedded computer systems for many years to come.

An example of a hybrid backplane for a soft transition from the conventional slots, supported by the parallel PCI bus, to pure, serial CPCI Plus slots is shown in Fig. 2. It can be clearly seen that the peripheral slots require, unlike in CompactPCI, only a relatively small, low-cost connector with six rows of contacts. It carries power, high-speed signals and, where used, monitoring and control lines.

As was previously common, up to 7 parallel peripheral slots and up to 4 serial peripheral CompactPCI Plus slots can be supported on PICMG 2.30 CPLUS I/O-based systems. The restriction to 4 slots results from the number of contacts available in the P2 connector. Here again, however, the number of connectors can be increased if required by the method already described. Not all signals such as PCIe, SATA, Ethernet and USB need to be available on a single peripheral slot. The pinout for the P2 connector of the system slot was defined in such a way that accidental wrong insertion, e.g. of a 64-bit CPU into a PICMG 2.30 CPLUS I/O slot or vice versa, does not cause damage to the respective boards.

It is therefore not necessary for "old" CompactPCI boards to be redesigned immediately; they can go on being produced for as long as the chips for the parallel PCI bus continue to be available. New designs should, however, then be drafted on the basis of CompactPCI Plus. The PICMG 2.30 CPLUS I/O slot joins the two worlds together.